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cy7c1011cv33 2-mbit (128 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05232 rev. *l revised june 7, 2011 2-mbit (128 k 16) static ram features temperature ranges ? industrial: ?40 c to 85 c ? automotive-a: ?40 c to 85 c ? automotive-e: ?40 c to 125 c pin and function compatible with cy7c1011bv33 high speed ? t aa = 10 ns (industrial and automotive-a) ? t aa = 12 ns (automotive-e) low active power ? 360 mw (max) (industrial and automotive-a) 2.0 v data retention automatic power down when deselected independent control of upper and lower bits easy memory expansion with chip enable (ce) and output enable (oe ) features available in pb-free 44-pin thin small outline package (tsop) ii, 44-pin thin quad flat package (tqfp) , and non pb-free 48-ball very fine-pitch ball grid array (vfbga) packages functional description the cy7c1011cv33 is a high performance complementary metal oxide semiconductor (cmos) static ram organized as 131,072 words by 16 bits. this device has an automatic power down feature that significantly reduces power consumption when deselected. to write to the device, take ce and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 16 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 16 ). to read from the device, take ce and oe low while forcing the write enable (we ) high. if ble is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . for more information, see the truth table on page 10 for a complete description of read and write modes. the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low and we low). 128 k x 16 ram array i/o 0 ?i/o 7 row decoder a 0 a 1 a 2 a 3 a 6 column decoder a 10 a 11 a 12 a 13 a 14 sense amps input buffer oe a 4 a 5 i/o 8 ?i/o 15 we ble bhe a 15 a 8 a 7 a 16 ce a 9 logic block diagram [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 2 of 17 contents pin configuration ............................................................. 3 selection guide ................................................................ 4 maximum ratings ............................................................. 5 operating range ............................................................... 5 electrical characteristics ................................................. 5 capacitance ...................................................................... 6 thermal resistance .......................................................... 6 ac test loads and waveforms ....................................... 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 10 ordering information ...................................................... 11 ordering code definitions ..... .................................... 11 package diagrams .......................................................... 12 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc solutions ......................................................... 17 [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 3 of 17 pin configuration figure 1. 44-pin tsop ii [1] figure 2. 48-ball vfbga pinout [1] figure 3. 44-pin tqfp 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 14 a 15 a 8 a 9 a 10 a 11 a 12 a 13 nc oe bhe ble ce we i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 v cc v cc v ss v ss nc 10 a 16 we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe nc nc a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss we v cc a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 nc a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 4 nc 1 a 16 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 note 1. nc pins are not connected on the die. [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 4 of 17 selection guide description -10 -12 unit maximum access time 10 12 ns maximum operating current industrial 100 95 ma automotive-a 100 ? ma automotive-e ? 120 ma maximum cmos standby current industrial 10 10 ma automotive-a 10 ? ma automotive-e ? 15 ma [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 5 of 17 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc relative to gnd [2] .....?0.5 v to +4.6 v dc voltage applied to outputs in high z state [2] .................................. ?0.5 v to v cc + 0.5 v dc input voltage [2] ............................... ?0.5 v to v cc + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage .......................................... > 2001 v (mil-std-883, method 3015) latch up current ..................................................... > 200 ma operating range range ambient temperature (t a ) v cc industrial ?40 ? c to +85 ? c 3.3 v ? 10% automotive-a ?40 ? c to +85 ? c automotive -e ?40 ? c to +125 ? c electrical characteristics over the operating range parameter description test conditions -10 -12 unit min max min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ?0.4?0.4 v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc industrial ?1 +1 ?1 +1 ? a automotive-a ?1 +1 ? ? automotive-e ? ? ?20 +20 i oz output leakage current gnd < v i < v cc , output disabled industrial ?1 +1 ?1 +1 ? a automotive-a ?1 +1 ? ? automotive-e ? ? ?20 +20 i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc industrial ? 100 ? 95 ma automotive-a ? 100 ? ? automotive-e ? ? ? 120 i sb1 automatic ce power down current ?ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max industrial ? 40 ? 40 ma automotive-a ? 40 ? ? automotive-e ? ? ? 45 i sb2 automatic ce power down current ? cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 industrial ? 10 ? 10 ma automotive-a ? 10 ? ? automotive-e ? ? ? 15 note 2. v il (min) = ?2.0 v for pulse durations of less than 20 ns. [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 6 of 17 capacitance parameter [3] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 8 pf c out output capacitance 8pf thermal resistance parameter [3] description test conditions 44-pin tsop ii 44-pin tqfp 48-ball vfbga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 44.56 42.66 46.98 ? c/w ? jc thermal resistance (junction to case) 10.75 14.64 9.63 ? c/w ac test loads and waveforms figure 4. ac test loads and waveforms [4] 90% 10% 3.0 v gnd 90% 10% all input pulses 3.3 v output 30 pf* * capacitive load consists of all components of the test environment (b) r 317 ?? r2 351 ?? rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 ? 50 ? 1.5 v (c) (a) 3.3 v output 5 pf (d) r 317 ?? r2 351 ?? 10-ns devices: 12-ns devices: high-z characteristics: notes 3. tested initially and after any design or proce ss changes that may affect these parameters. 4. ac characteristics (except high z) for 10-ns pa rts are tested using the load conditions shown in figure 4 (a). all other speeds are tested using the thevenin load shown in figure 4 (b). high z characteristics are tested fo r all speeds using the test load shown in figure 4 (d). [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 7 of 17 switching characteristics over the operating range parameter [5] description -10 -12 unit min max min max read cycle t power [6] v cc (typical) to the first access 1 ? 1 ? ? s t rc read cycle time 10 ? 12 ? ns t aa address to data valid ? 10 ? 12 ns t oha data hold from address change 3 ? 3 ? ns t ace ce low to data valid ? 10 ? 12 ns t doe oe low to data valid industrial/automotive-a ? 5 ? 6 ns automotive-e ? ? ? 8 t lzoe oe low to low z [7] 0?0?ns t hzoe oe high to high z [7, 8] ?5?6ns t lzce ce low to low z [7] 3?3?ns t hzce ce high to high z [7, 8] ?5?6ns t pu ce low to power up 0 ? 0 ? ns t pd ce high to power down ? 10 ? 12 ns t dbe byte enable to data valid i ndustrial/automotive-a ? 5 ? 6 ns automotive-e ? ? ? 8 t lzbe byte enable to low z 0 ? 0 ? ns t hzbe byte disable to high z ? 5 ? 6 ns write cycle [9, 10] t wc write cycle time 10 ? 12 ? ns t sce ce low to write end 7 ? 8 ? ns t aw address setup to write end 7 ? 8 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 7 ? 8 ? ns t sd data setup to write end 5 ? 6 ? ns t hd data hold from write end 0 ? 0 ? ns t lzwe we high to low z [7] 3?3?ns t hzwe we low to high z [7, 8] ?5?6ns t bw byte enable to end of write 7 ? 8 ? ns notes 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, and input pulse levels of 0 to 3.0 v. 6. t power gives the minimum amount of time that the power supply is at typical v cc values until the first memory access is performed. 7. at any temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 8. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (d) of figure 4 on page 6 . transition is measured ? 500 mv from steady state voltage 9. the internal write time of the memory is defined by the overlap of ce low, we low, and bhe /ble low. ce , we , and bhe /ble must be low to initiate a write. the transition of these signals terminate the write. the input da ta setup and hold timing is referenced to the leading edge of the signal that terminates the write. 10. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 8 of 17 switching waveforms figure 5. read cycle no. 1 (address transition controlled) [11, 12] figure 6. read cycle no. 2 (oe controlled) [12, 13] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd t dbe t lzbe t hzce high impedance i cc i sb oe ce address data out v cc supply bhe ,ble current notes 11. device is continuously selected. oe , ce , bhe , and/or ble = v il . 12. we is high for read cycle. 13. address valid prior to or coincident with ce transition low. [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 9 of 17 figure 7. write cycle no. 1 (ce controlled) [14, 15] figure 8. write cycle no. 2 (ble or bhe controlled) switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw t data io address ce we bhe ,ble t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble ce we notes 14. data i/o is high impedance if oe, bhe , and/or ble = v ih . 15. if ce goes high simultaneously with we going high, the output remains in a high impedance state. [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 10 of 17 figure 9. write cycle no. 3 (we controlled, low) truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high z high z power down standby (i sb ) l l h l l data out data out read ? all bits active (i cc ) l l h l h data out high z read ? lower bits only active (i cc ) l l h h l high z data out read ? upper bits only active (i cc ) l x l l l data in data in write ? all bits active (i cc ) l x l l h data in high z write ? lower bits only active (i cc ) l x l h l high z data in write ? upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw t sa t lzwe t hzwe data i/o address ce we bhe ,ble [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 11 of 17 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 10 CY7C1011CV33-10ZSXA 51-85087 44-pin tsop ii (pb-free) automotive-a 12 cy7c1011cv33-12axi 51-85064 44-pin tqfp (pb-free) industrial cy7c1011cv33-12zsxe 51-85087 44-pin tsop ii (pb-free) automotive-e cy7c1011cv33-12bvxe 51-85150 48-ball (6 8 1 mm) vfbga temperature range: x = a or i or e a = automotive-a; i = indu strial; e = automotive-e pb-free package type: xx = zs or a or bv zs = 44-pin tsop ii a = 44-pin tqfp bv = 48-ball vfbga speed grade: xx = 10 ns or 12 ns v33 = 3.3 v process technology: 150 nm bus width: 16 bits density: 2-mbit fast asynchronous sram family technology code: c = cmos marketing code: 7 = sram company id: cy = cypress 7 cy 1 - xx xx x c v33 x 1 01 c [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 12 of 17 package diagrams figure 10. 44-pin tsop z44-ii, 51-85087 51-85087 *c [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 13 of 17 figure 11. 44-pin tqfp (10 10 1.4 mm) a44s, 51-85064 package diagrams (continued) 51-85064 *e [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 14 of 17 figure 12. 48-ball vfbga (6 8 1 mm) bv48/bz48, 51-85150 package diagrams (continued) 51-85150 *e 51-85150 *f [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 15 of 17 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable sram static random access memory tqfp thin quad flat pack tsop thin small outline package ttl transistor-transistor logic vfbga very fine-pitch ball gird array we write enable symbol unit of measure c degree celsius mhz mega hertz a micro amperes s micro seconds ma milli amperes mm milli meter ms milli seconds mv milli volts mw milli watts ns nano seconds % percent pf pico farad vvolts wwatts [+] feedback
cy7c1011cv33 document number: 38-05232 rev. *l page 16 of 17 document history page document title: cy7c1011cv33, 2-mbit (128 k 16) static ram document number: 38-05232 rev. ecn no. issue date orig. of change description of change ** 117132 07/31/02 hgk new data sheet *a 118057 08/19/02 hgk pin configurat ion for 48-ball fbga correction *b 119702 10/11/02 dfp updated fbga to vfbga; updated package code on page 8 to bv48a. updated address pinouts on page 1 to a0 to a16. updated cmos standby current on page 1 from 8 to 10 ma *c 386106 see ecn pci added lead-free parts in ordering information table *d 498501 see ecn nxr corrected typo in the logic block diagram on page# 1 included the maximum ratings for static discharge voltage and latch up current on page# 3 changed the description of i ix from input load current to input leakage current in dc elec trical characteristics table updated the ordering information table *e 522620 see ecn vkn added thermal resistance table *f 1891366 see ecn vkn/aesa added -10zsxa part updated ordering information table *g 2428606 see ecn vkn/pyrs corrected typo in the 44-pin tsop and 48-ball fbga pinout removed commercial parts removed 15 ns speed bin removed inactive parts from the ordering information table *h 2664421 02/25/09 vkn/aesa added automotive-e specs for 12 ns speed updated ordering information table *i 2898399 03/24/2010 kao/aju updated package diagrams *j 2950666 06/11/2010 vkn include d ?cy7c1011cv33-12bvxe? in ordering information added contents and acronyms updated sales, solutions, and legal information added ordering code definitions . *k 3089939 11/13/2010 pras removed inactive part from ordering information. *l 3276463 06/07/2011 kao updated functional description (removed ?for best practice recommendations, refer to the cypress application note an1064, sram system guidelines.?). added units of measure . updated package diagrams . updated in new template. [+] feedback
document number: 38-05232 rev. *l revised june 7, 2011 page 17 of 17 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1011cv33 ? cypress semiconductor corporation, 2002-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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